The present invention relates to semiconductor devices and manufacturing methods thereof, and more particularly, to a technique effectively applied to a semiconductor device including a MISFET and using a stress film, and a manufacturing method thereof.
Various measures have been currently taken to miniaturize transistors, thereby improving the performance of the transistors. However, the improvement of the performance of the transistor only by the miniaturization has a problem of an increase in cost as compared to the performance.
For this reason, a new method has been proposed to improve the performance of the transistor using a stress film, typified by a nitride film, in addition to the improvement of the performance of the transistor only by the miniaturization.
Japanese Unexamined Patent Publication No. 2009-111067 (Patent Document 1) discloses a technique that performs plasma processing on a stress distortion generating film formed over a semiconductor substrate.
Japanese Unexamined Patent Publication No. 2008-103504 (Patent Document 2) discloses a technique that involves forming a liner SiN film so as to cover a gate electrode, a source region, and a drain region, and applying ultraviolet rays to the liner SiN film.
Japanese Unexamined Patent Publication No. 2008-147325 (Patent Document 3) discloses a technique that involves forming a silicon nitride film and a silicon oxide film in that order to cover a gate structure of an NMON transistor and a gate structure of a PMOS transistor, and irradiating the silicon nitride film in an NMOS region with ultraviolet rays.
C. D. Sheraw et al., 2005 Symposium on VLSI Technology Digest of Technical Papers, p. 12-p. 13 (Non-Patent Document 1) discloses a technique regarding a dual stress liner which involves forming a silicon nitride film having a tensile stress so as to cover an n-channel MOSFET, and forming a silicon nitride film having a compressive stress so as to cover a p-channel MOSFET.